1. Field of the Invention
The present invention relates generally to integrated circuit technology, and, more specifically, the present invention relates to the testing of an integrated circuit.
2. Background Information
Integrated circuits are becoming more densely packed with increasing numbers of individual circuit elements. In fact, it is common for a single chip to have thousands of individual elements that include millions of transistors. One way of testing the circuit elements in an integrated circuit is performed by generating a test pattern and applying the test pattern to the inputs of the integrated circuit using mux scan flip-flops. Depending on the test pattern, the responses of the integrated circuit to the test pattern can provide an accurate indication of the existence or non-existence of defects.
During a typical testing sequence, a scan mode signal, also known as a scan enable signal, is sent to the integrated circuit to effect either system mode or test mode. In system mode, the integrated circuit functions as it normally does, while in test mode, the integrated circuit receives test patterns and performs other test operations. However, because of the continuing trend of increasing integrated circuit speeds and increasing device density, it is becoming increasingly difficult to send scan mode signals to all of the mux scan flip-flops in one system clock cycle. In addition, it is generally more difficult to test for timing-related defects, delay defects or transition defects using present day mux scan flip-flop implementations.
For instance, as depicted in the test circuit of FIG. 1, mux scan flip-flops 6, 12, 19, 25 and 31 are coupled to a single tester pin 1 via scan mode inputs 2, 8, 15, 21 and 27, respectively. A test pattern input 9 of mux scan flip-flop 12 is coupled to a data output 7 of mux scan flip-flop 6. Data outputs 7 and 13 are coupled to an integrated circuit logic 14. Data inputs 17, 23 and 29 of mux scan flip-flops 19, 25 and 31, respectively, are coupled to integrated circuit logic 14. A test pattern input 28 of mux scan flip-flop 31 is coupled to a data output 26 of mux scan flip-flop 25, and a test pattern input 22 of mux scan flip-flop 25 is coupled to a data output 20 of mux scan flip-flop 19.
FIG. 2 illustrates the components of a mux scan flip-flop used in the test circuit of FIG. 1. With specific reference to mux scan flip-flop 6, FIG. 2 depicts a first stage 42, which can be a master flip-flop, coupled to an output 40 of a multiplexor 41 via a value input 46. A clock input 48 of first stage 42 is coupled to an output 39 of an inverter 38. A value output 43 of first stage 42 is coupled to a value input 47 of second stage 45, which can be a slave flip-flop. A value output 30 of second stage 45 acts as the data output 7 of mux scan flip-flop 6.
With reference to FIG. 1, tester pin 1 sends a scan mode signal with a logical value of either zero or one to mux scan flip-flops 6, 12, 19, 25 and 31, where a value of zero indicates an inactive scan mode signal and a value of one indicates an active scan mode signal. Specifically, a value of zero sets mux scan flip-flops 6, 12, 19, 25 and 31 to system mode, while a value of one sets mux scan flip-flops 6,12, 19, 25 and 31 to scan enable mode. It should be emphasized that with an increasing number of mux scan flip-flops being disposed in integrated circuits and with continually increasing integrated circuit speeds, the scan mode signal takes more than one clock cycle to reach all of the mux scan flip-flops. In scan enable mode, at the beginning of a test sequence, mux scan flip-flops 6 and 19 receive the first bit of an N bit test pattern via test pattern inputs 3 and 16, respectively. N is the number of mux scan flip-flops in the scan chain that is receiving the test pattern. To illustrate, one scan chain in FIG. 1 includes mux scan flip-flops 6 and 12, making N equal to two, and a second scan chain includes mux scan flip-flops 19, 25 and 31, making N equal to three.
Mux scan flip-flops 6, 12, 19, 25 and 31 receive clock signals via a clock signal input 5 from clock signal pad 33. After one clock cycle, the first bit of the two bit test pattern sent to mux scan flip-flop 6 is ready to be latched in by mux scan flip-flop 12, to which the first bit was sent via data output 7 and test pattern input 9. During the next clock cycle, the second bit of the two bit test pattern is latched into mux scan flip-flop 6, and the first bit is latched into mux scan flip-flop 12. After that clock cycle, tester pin 1 sets mux scan flip-flops 6, 12, 19, 25 and 31 to system mode so that they can latch in data via data inputs 4, 10, 17, 23 and 29, respectively. Once system mode has been established, one clock cycle is needed to send the first and second bits from mux scan flip-flops 12 and 6, respectively, to integrated circuit logic 14 and to capture or latch in test output data from integrated circuit logic 14 into mux scan flip-flops 19, 25 and 31 via data inputs 17, 23 and 29, respectively. After the test output data is latched in, tester pin 1 sets mux scan flip-flops 6, 12, 19, 25 and 31 back to scan enable mode. Finally, the test output data captured in mux scan flip-flops 19, 25 and 31 is unloaded via scan output 24 in three more clock cycles, one for each mux scan flip-flop in that scan chain.
A limitation of present day test circuits such as the one depicted in FIG. 1 is that the mux scan flip-flops are generally restricted to identifying stuck-at faults in the integrated circuit. In stuck-at fault testing, the integrated circuit and the test patterns are generally clocked at speeds slower than the system clock speed, which means that timing-related defects are not identified. Thus, what is desired is a method and apparatus for utilizing mux scan flip-flops to test for speed-related defects in integrated circuits. Such a method and apparatus should be able to detect the speed-related defects in an integrated circuit without consuming excessive amounts of power.